Advantest Corporation - ADR

SoC tester market outlook revised higher (structural AI-driven growth) - Management said the SoC TAM increase to $11B midpoint (from $9.1B) is mostly driven by growth in inference/“compute” applications rather than a shift toward a single device type. - Demand is strong across CPU, GPU, and custom ASIC (they explicitly said they see acceleration in all), with inference applications the biggest driver of the TAM change. - Sustainability: they stated demand is expected to remain sustainable throughout this year and into next year, not just a short-cycle bump.

Test content & complexity expansion is a major TAM driver (more inserts, longer times, accelerator complexity) - Incremental TAM is supported by (1) higher test content over time, (2) longer test times, and (3) more test insertions. - Particularly emphasized: accelerator/advanced packaging (e.g., 3D packaging) increases final-package test complexity, so accelerators have higher back-end test intensity than CPU packages. - At wafer sort, CPU vs monolithic chip testing is more similar, but final package test is materially higher on accelerator side (no exact numbers provided).

Capacity expansion: moving faster, but guided by supply-chain constraints (especially advanced packaging) - They reiterated a plan to expand 93000 tester capacity to 10,000 units per year by end of 2028 / early 2029, but said they are pulling that target in (new date to be provided next quarter). - 5,000-unit milestone: management indicated they are on track and likely already flowing through 5,000 (so the question is mainly the next step to 10,000+). - Key constraint logic investors should note: scaling isn’t just unit testers; it must match more wafer starts + more advanced packaging + rising test content generation/complexity. They also stressed they plan with buffer to avoid being a “critical path” for customers.