Cadence Design Systems, Inc.

Strong Q3 performance + record backlog; results beat guidance - Q3 revenue: $1.633B (+22% YoY), with double-digit growth across all product groups. - Record backlog: $8.2B; reflects “strong bookings” and “growing customer demand.” - Profitability: GAAP operating margin 26.2% and non-GAAP 44.1%; GAAP EPS $1.05, non-GAAP EPS $2.11. - Surprise / positive: Management emphasized momentum across *both* traditional EDA/IP and the newer Agentic AI portfolio—suggesting AI is not just narrative, but feeding into usage and demand for base products.

Updated 2026 outlook raised; continued margin strength - 2026 revenue outlook (updated): $6.387B–$6.417B (midpoint implies ~21% growth vs prior year baseline cited by management). - 2026 EPS outlook raised by $0.30 to GAAP EPS $4.84–$4.90 and non-GAAP EPS $8.37–$8.43 (midpoint: $8.40). - Operating margins: GAAP 28.2%–29.2%, non-GAAP 44.2%–45.2%. - Q4 guidance: revenue $1.695B–$1.725B, GAAP EPS $1.23–$1.29, non-GAAP EPS $2.19–$2.25; non-GAAP margin ~44%–45%. - Expectation: recurring/ratable model should remain resilient given ongoing customer R&D spend and increasing design activity.

Agentic AI commercialization: “Maestro” + evidence of measurable customer productivity - Launch: Maestro, a portfolio of domain-specialized models for chip/system design, integrated into Cadence’s agent framework using a 3-layer approach: - Top: AI agents & orchestration (agent “super agents”) - Middle: Cadence’s physically accurate simulation/optimization engine - Bottom: accelerated compute + proprietary data - Key performance claims: up to 30% higher quality and up to 5x better token efficiency vs general-purpose foundation models; model routing selects the best model per task. - Monetization framing (high level): no explicit price disclosure, but management connected Agentic AI to recurring revenue growth and increased usage of core EDA tools (i.e., agent value drives more seat/usage-like consumption of base software). - Early traction examples cited: - RTL generation (ChipStack): ~24% area / 18% power reduction vs foundation-model-only code (customer: Honda). - MediaTek (verification coverage): 50–70% improvement and 1.4x–2x less engineering effort after deploying ChipStack in production DV. - InnoStack productivity: 34x for Renesas MCU team; Samsung used it to speed PPA exploration. - AuraStack: Nokia reported 5x acceleration on key workflows (on-prem secure compute).